The present invention relates to an output buffer.
Conventionally, a communication interface between a computer and its peripheral device is established by providing input/output buffers on the bus lines.
FIG. 5 shows a conventional input/output P- and n-channel transistors 4 and 5 constitute an output buffer. A NAND circuit 1, inverter 2, and NOR circuit 3 constitute a circuit for controlling the output buffer. Table 1 shows normal operation of this input/output buffer.
TABLE 1 ______________________________________ Normal Operation of Input/Output Buffer State EN OUT A B C Tr4 Tr5 IO IN ______________________________________ 1 0 x H H L Off Off Z x 2 0 x H H L Off Off 1 1 3 0 x H H L Off Off 0 0 4 1 1 L L L On Off 1 1 5 1 0 H L H Off On 0 0 ______________________________________
In Table 1, EN denotes an enable signal for changing the output buffer to an enable state (an input buffer 6 to a disable state); OUT, a signal to be sent to a target device 51 such as a computer; IO, a signal appearing at an input/output terminal 10; IN, an output signal from the input buffer 6; A, an output signal from the NAND circuit 1; B, an output signal from the inverter 2; C, an output signal from the NOR circuit 3; Tr4 and Tr5, the states of transistors 4 and 5; "x", the absence of any signal input/output; and "Z", a high-impedance state.
The input/output buffer in FIG. 5 functions as an input buffer for an enable signal of "0" (states 1 to 3 in Table 1), and as an output buffer for an enable signal EN of "1" (states 4 and 5 in Table 1).
Operation when a board 52 having the input/output buffer is inserted into the target device 51 will be described. Assume that the target device 51 is a computer, and the board 52 having the input/output buffer is an interface board for connecting the computer and peripheral device. A power supply voltage VDD of the board 52 is supplied from the target device when the board 52 is inserted into the target device 51.
Table 2 shows operation of the input/output buffer immediately after the board 52 is inserted into the target device 51 while the target device 51 is ON.
TABLE 2 ______________________________________ Operation of Input/Output Buffer Upon Inserting Hot Line State EN OUT A B C Tr4 Tr5 IO IN ______________________________________ 6 x x L L L On Off H x ______________________________________
Table 2 shows the state before the power supply voltage VDD rises to a sufficient value. The output signal A from the NAND circuit 1, the output signal B from the inverter 2, and the output signal C from the NOR circuit 3 are at "L" level. Thus, the p-channel transistor 4 is turned on, whereas the n-channel transistor 5 is turned off.
When a terminal of the target device corresponding to the input/output terminal 10 of the board 52 is at "H" level, a large current I like the one shown in FIG. 5 flows from the target device 51 to power supply of the board 52 via the input/output terminal 10 and p-channel transistor 4.
This large current I may destruct a driver (output buffer) 53 of the target device 51 or a circuit (not shown) such as a regulator arranged on the power supply line of the board 52.
In this manner, the conventional input/output buffer may damage the circuit of the target device or the circuit of the board upon inserting a hot line. This problem does not occur in a target device which allows inserting the board after OFF operation. However, some target devices are difficult to turn off. Accordingly, there is provided a hot-line insertion/removal method capable of removing/inserting a board from/into a target device without turning off the target device such as a computer (e.g., Japanese Patent Laid-Open No. 5-37169).
FIG. 6 shows the arrangement of a hot-line insertion/removal method disclosed in Japanese Patent Laid-Open No. 5-37169. A backboard (corresponding to the target device 51 in FIG. 5) 43 allows mounting a plurality of circuit boards (corresponding to the board 52 in FIG. 5) 44. The backboard 43 has signal lines for connecting the circuit boards 44. The backboard 43 and each circuit board 44 respectively have connectors 11 and 38. The connector 11 comprises a ground pin 12, signal pin 13, and power supply pins 14 and 15. The ground pin 12 and power supply pin 14 are long pins, and the signal pin 13 and power supply pin 15 are short pins. In inserting the circuit board 44 into the backboard 43, the ground pin 12 and power supply pin 14 are connected to corresponding pins 39 and 41 of the backboard 43 earlier than the signal pin 13 and power supply pin 15, and in removal, connected later than the signal pin 13 and power supply pin 15.
The case in which the circuit board 44 is removed and to be inserted into the backboard 43 while the backboard 43 is ON will be explained.
When the circuit board 44 is inserted into the backboard 43, the ground pin 12 and power supply pin 14 of the circuit board 44 are connected to the corresponding pins 39 and 41 of the backboard 43. Upon connection, the power supply pin 14 receives power to operate a power-on clear circuit (PCLR) 20. The power-on clear circuit (PCLR) 20 sends an initialization signal of a predetermined period to an AND circuit 28. The output of the AND circuit 28 is connected to a reset terminal 31 of a flip-flop 29. If a signal at the reset terminal 31 is enabled, an output from an inverting output terminal 30 of the flip-flop 29 changes to "1". The output of the inverting output terminal 30 is connected to enable terminals 18 and 19 of output and input buffers 16 and 17 via an OR circuit 23. Since signals at the enable terminals 18 and 19 are "1", the outputs of the output and input buffers 16 and 17 change to a high-impedance state. Then, the output and input buffers 16 and 17 are disconnected from the backboard 43. At this time, an inverted output from the flip-flop 29 is input to a NOT circuit 36 to turn on a light-emitting diode 37, thereby representing a disconnected state.
The circuit board 44 is further inserted, the signal pin 13 and power supply pin 15 are connected to corresponding pins 40 and 42 of the backboard 43. The power supply pin 15 receives power to operate a power-on clear circuit (PCLR) 21. The power-on clear circuit (PCLR) 21 outputs an initialization signal of a predetermined period to the AND circuit 28. As a result, the reset terminal 31 of the flip-flop 29 is kept enabled until the initialization signal from the power-on clear circuit 21 is disabled, thereby inhibiting input of any signal from a switch 35. If the operator depresses the unlocked switch 35 upon completion of insertion of the circuit board 44, the depression signal is input to a clock terminal 33 of the flip-flop 29 via a switch chattering prevention (CHT) circuit 34. Until the depression signal is input to the clock terminal 33, an output from the inverting output terminal 30 is kept "1". Since the inverting output terminal 30 is connected to a data input terminal 32, the output from the inverting output terminal 30 changes to "0" upon reception of the depression signal at the clock terminal 33. Consequently, the enable signal terminals 18 and 19 of the output and input buffers 16 and 17 are enabled to connect the output and input buffers 16 and 17 to the backboard 43. Since the output from the inverting output terminal 30 of the flip-flop 29 is "0", the light-emitting diode 37 is turned off to represent a connected state.
This hot-line insertion/removal method disclosed in Japanese Patent Laid-Open No. 5-37169 can prevent destruction of the device upon inserting/removing a hot line. However, the circuit is complicated to increase the cost.